1. Field of the Invention
The present invention relates generally to an apparatus and method for correcting an error in data read from a recording medium which stores data. More particularly, this invention relates to an apparatus and a method to detect and correct errors contained in data used in recording and reproducing system which uses an optical disk as a recording medium.
2. Description of the Related Art
Data transfer rates between optical disk recording and reproduction devices and their host processors have undergone a significant increases over the past number of years. Accompanying this increase has been a demand for increased operational speeds of devices used to defect and correct errors occurring in the data transferred between the disk recording and reproduction devices and their host processors.
In this technology, the term "optical disk" means a disk type recording medium onto and from which data can be written and read using the optical technology. An optical disk has a plurality of data storage areas called "sectors". FIG. 1 shows a conventional data correcting apparatus for use in an optical disk system. This data correcting apparatus comprises a formatter circuit 1, a buffer memory controller 2, a syndrome generator 3, a reducer circuit 5, a Chien search circuit 6, a buffer memory 7, and an interface circuit 8. The formatter circuit 1, buffer memory controller 2, syndrome generator 3, reducer circuit 5 and Chien search circuit 6 are controlled by a microprocessor 4.
The formatter circuit 1 receives read data from an optical disk data reading apparatus (not shown) via the interface circuit 8. In this case, data recorded on an optical disk is coded based on Cross Interleave Reed Solomon coding. When receiving the coded read data from the data reading apparatus, the formatter circuit 1 decodes the read data and outputs the decoded data to the buffer memory controller 2 and the syndrome generator 3. The decoded data includes an ECC (Error Checking and Correcting) code which is used to detect and correct for errors contained in the data.
Based on the decoded data and the ECC code, the syndrome generator 3 generates an ECC syndrome, a data matrix, based on the Cross Interleave Reed Solomon code (CIRC). The ECC syndrome has a matrix type data structure, and is produced only when the decoded data contains an error. The syndrome generator 3 has a status register 3a. When two sectors of decoded data are output to the syndrome generator 3 from the formatter circuit 1 and after one sector of ECC syndromes has been generated, a flag is set to "1" in the status register 3a. The microprocessor 4 then reads one sector of the ECC syndromes generated by the syndrome generator 3, and writes it to the reducer circuit 5.
The reducer circuit 5 then computes the coefficients in a polynomial equation for determining the position of an error and in a polynomial equation for obtaining an error value based on CIRC. The reducer circuit 5 also has a status register 5a. Following the computational operation performed by the reducer circuit 5 based on the ECC syndromes, a flag is set to "1" in the status register 5a. The microprocessor 4 next reads the computed coefficients of an error position polynomial equation and an error value polynomial equation from the reducer circuit 5, and writes the coefficients in the Chien search circuit 6.
Utilizing the coefficients output from the reducer circuit 5, the Chien search circuit 6 computes the error value and error position of the decoded data. Based on the computed error value, the Chien search circuit 6 computes a CRC (Cyclic Redundancy Check) syndrome for error detection.
The Chien search circuit 6 has a status register 6a. When the computations for the error position and error value in the Chien search circuit 6 are completed, the flag in the status register 6a is set to "1". Given this value of the flag in the status register 6a, the microprocessor 4 reads the computed error value and error position from the Chien search circuit 6.
Based on a command from the microprocessor 4, the buffer memory controller 2 stores the decoded data from the formatter circuit 1 into the buffer memory 7, and outputs data stored in the buffer memory 7 to the microprocessor 4.
FIG. 2 illustrates a flowchart depicting the operation of this data correcting apparatus. When read data from the data reading apparatus is input to the formatter circuit 1, the formatter circuit 1 decodes the read data and outputs the decoded data to the buffer memory controller 2 and the syndrome generator 3. The buffer memory controller 2 stores the received decoded data in the buffer memory 7.
At step 1, the microprocessor 4 determines if the flag set in the status register 3a is "1", i.e., if one sector of ECC syndromes has been generated by the syndrome generator 3. When the flag's value changes to "1", the microprocessor 4 reads that one sector of ECC syndromes (step 2) and writes the ECC syndromes in the reducer circuit 5 (step 3).
At step 4, the microprocessor 4 activates the reducer circuit 5 to compute the coefficients of an error position polynomial equation and of an error value polynomial equation based on the ECC syndromes sent to the reducer circuit 5 from the syndrome generator 3.
At step 5, the microprocessor 4 determines if the flag set in the status register 5a of the reducer circuit 5 is "1", i.e., if the computation in the reducer circuit 5 is complete. When the flag's value changes to "1", the microprocessor 4 reads the error position coefficients and the error value coefficients from the reducer circuit 5 at step 6.
The microprocessor 4 writes the read coefficients in the Chien search circuit 6 at step 7, and activates the Chien search circuit 6 at step 8. At step 9, the microprocessor 4 determines if the flag set in the status register 6a of the Chien search circuit 6 is "1", i.e., if the computations in the Chien search circuit 6 are complete. When the flag's value changes to "1", the microprocessor 4 reads the computed error position and value from the Chien search circuit 6 at step 10.
Based on the read error position information determined at step 11, the microprocessor 4 then computes an address in the buffer memory 7 where the data contains an error. The microprocessor then outputs a read command to the buffer memory controller 2 to read error data stored at that address in the buffer memory 7 at step 12.
When the error data reading operation of the microprocessor 4 is completed at step 13, the microprocessor 14 corrects the read decoded data containing an error based on the error value information. At step 15, the microprocessor 4 writes the corrected data in the buffer memory 7 via the buffer memory controller 2.
In parallel to the operations at steps 10 to 15, the microprocessor 4 generates a CRC syndrome and computes CRC data using the CRC syndrome to determine if the result of the error correction is correct. Through the above-described sequence of operations, the correction of one sector of decoded data is completed.
In the data correcting apparatus, the microprocessor 4 always monitors the flags in the status registers 3a, 5a and 6a in the syndrome generator 3, reducer circuit 5 and Chien search circuit 6. When each flag is set to "1", the microprocessor 4 issues instructions to carry out subsequent operations. Due to this, there is a relatively long wait time from the end of the computation in each of the circuits 3, 5 and 6 to the next operation.
Due to the constant monitoring of the above-mentioned flags, the microprocessor 4 must devote a significant amount of processing time just to flag monitoring. This places constraints on the amount of processing which the microprocessor 4 can devote to other operations, and in effect, results in a loss of processing speed.
To execute decoded data correction in the buffer memory 7, the microprocessor 4 accesses the buffer memory 7 via the buffer memory controller 2. The time the microprocessor 4 requires to access the memory 7 further detracts from the processing time available to other operations. This delays the other operations of the microprocessor 4 than the accessing operation.
The CRC syndrome generated in the Chien search circuit 6 is read out by the microprocessor 4 and is used in a predetermined computation to obtain CRC data. The time required by the microprocessor 4 to make the necessary computations based on the CRC syndrome, also detracts from other operations of the microprocessor 4 and effectively decreases the processing reserve of the microprocessor 4.